A 1.0 GHz clock generator design with a negative delay using a single-shot locking method

A high-speed digital clock generator circuit is presented to provide negative delays in order to avoid a multi-locking hazard. The negative delay also results in small power consumption and shorter access time if the proposed circuit is used in the clock generator circuit of memory devices. Meanwhile, an accurately locked clock signal is also provided. The locked clock signal can be as high as 1.0 GHz at the presence of a random noise with 10% of power supply voltage while the design is implemented by 0.35 /spl mu/m CMOS 1P4M technology.