Frequency-hopping vernier clock generators for multiple clock domain SoCs

Proposed here is a new clock-distribution network for multiple clock domain SoCs, one that employs vernier clock generators. Although only one global-clock frequency is used, the clock frequency of individual IP cores can be varied. Furthermore, these variations can be conducted adaptively in fine increments under operating conditions, and clock signals can be stopped/restarted quickly (within a few cycles). These are important advantages for low-power sophisticated SoCs. This paper presents the vernier clock generator, the circuit which is key to making the clock-distribution network practical. A 1.0-GHz vernier clock generator employing a 90-nm CMOS technology is shown to successfully vary output from 0.5 to 1.0 GHz in 8 steps.