2013•대한전자공학회 학술대회Requires access
Multirate ΣΔ modulator를 위한 멀티 페이즈 논오버랩핑 클럭 발생기의 구현
양영태, 이현중, 조준수, 나승인, 김수환
Open publisher page 0 citations
Abstract
A multi-phase non-overlapping clock generator is essential circuit in multirate ΣΔ modulators. By improving conventional 2 phase non-overlapping clock generator, multi-phase non-overlapping clock generator is implemented in this paper. This paper also describes how to generate arbitrary non-overlapping clock with clock divider and combinational logic. Compared with 8 phase non-overlapping clock generator and the proposed clock generator, clock skew difference decreases 62.2%, but power consumption only increases 24.5%.