2009•Unpublished venueRequires access

A low-power programmable DLL-based clock generator with wide-range anti-harmonic lock

Yongtae Kim, Phi-Hung Pham, Woonhyung Heo, Jabeom Koo

Open publisher page 6 citations

Abstract

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13um CMOS technology. The proposed clock generator can generate a wide-range of the multiplied clock signals ranging from 125MHz to 2GHz. In addition, thanks to the proposed anti-harmonic lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019mm2and consumes 21mW at 2GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

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What this paper is about

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13um CMOS technology. The proposed clock generator can generate a wide-range of the multiplied clock signals ranging from 125MHz to 2GHz. In addition, thanks to the proposed anti-harmonic lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019mm2and consumes 21mW at 2GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

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OpenAlex reports 6 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.13um CMOS technology. The proposed clock generator can generate a wide-range of the multiplied clock signals ranging from 125MHz to 2GHz. In addition, thanks to the proposed anti-harmonic lock block, the clock generator can change the frequency dynamically in one cycle time of the reference clock. The proposed DLL-based clock generator occupies 0.019mm2and consumes 21mW at 2GHz. The ratio of power consumption to frequency of the proposed clock generator is smaller than those of conventional ones.

Key concepts: Clock generator, Clock gating, CPU multiplier, Clock domain crossing, Lock (firearm), Generator (circuit theory), Synchronous circuit, Digital clock manager

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