Technology mapping of speed-independent circuits based on combinational decomposition and resynthesis

This paper presents a solution to the problem of sequential multi#level logic synthesis of asynchronous speed#independent circuits. The starting point is a technology#independent speed#independent circuit ob# tained using# e.g.# the monotonous cover conditions. We describe an algorithm for the factorization of this circuit aimed at implementing it in a given standard cell library# while preserving speed#independence. The algorithm exploits known e#cient factorization tech# niques from combinational multi#level logic synthesis# but achieves also boolean simpli#cation. Experimen# tal results show a signi#cant improvement in terms of number and complexity of solvable circuits with respect to existing methods. 1 Introduction Recentyears have seen a revival of interest in the sub#class of asynchronous circuits called speed# independent circuits. Such circuits have been char# acterized by Muller in his seminal paper #9#asbe# ing hazard#free using the unbounded gate delay model . Even thou...