Optimal clock period FPGA technology mapping for sequential circuits

In this paper, we study the technology mapping problem for sequential circuits for LUTbased FPGAs.Existing approaches map the combinational logic between ip-ops (FFs) while assuming the positions of the FFs are xed.We study in this paper a new approach to the problem, in which retiming is integrated into the technology mapping process.We present a polynomial time technology mapping algorithm that can produce a mapping solution with the minimum clock period while assuming FFs can be arbitrarily repositioned by retiming.The algorithm has been implemented.Experimental results on benchmark circuits clearly demonstrate the advantage of our approach.For many benchmark circuits, our algorithm produced mapping solutions with clock periods not attainable by a mapping algorithm based on existing approaches, even when it employs an optimal delay mapping algorithm for combinational circuits.