A CMOS cell generation system for two-dimensional transistor placement

This paper presents an automatic layout generation system for CMOS uniform height cells with a two-dimensional layout style. The two-dimensional layout style described in this paper is effective with such cells as consist of considerably varied sizes of transistors. The proposed system generates a high density layout of such cells. To show the effectiveness of the two-dimensional layout style, we compared cell layouts generated by the proposed system with cell layouts in the traditional one-dimensional layout style, for various cell heights. Moreover, the experimental results show that the generated layouts are comparable in terms of cell area to manual two-dimensional layouts done by skilled layout designers.