AN AUTOMATIC CIRCUIT LAYOUT DESIGN FOR CMOS CELL
R Wang
Abstract
R Wang
Abstract
An automatic circuit layout design program for a CMOS cell ia described in this paper. It is a part df an automatic layout design system. It translates circuit descriptions of a cell into geometric descriptions of the cell layout. Its features are: routing of multi-port nets in the cell and assigning the ports around the cell are allowed, and the circuit layout of the cell is optimized. Therefore if the circuit description of a coll is inputed, the circuit layout file will bo generated automatically.
A significance statement is not available in the OpenAlex record.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
An automatic circuit layout design program for a CMOS cell ia described in this paper. It is a part df an automatic layout design system. It translates circuit descriptions of a cell into geometric descriptions of the cell layout. Its features are: routing of multi-port nets in the cell and assigning the ports around the cell are allowed, and the circuit layout of the cell is optimized. Therefore if the circuit description of a coll is inputed, the circuit layout file will bo generated automatically.
Key concepts: Design layout record, Computer science, Standard cell, IC layout editor, Physical design, Circuit extraction, Page layout, Integrated circuit layout