Technology scaling impact of variation on clock skew and interconnect delay

Variation has an increasingly negative impact on key interconnect applications, including clock skew and signal line delay. Here we consider both random and systematic variation in interconnect and device parameters as technology scales from 180 nm to 50 nm. For the case considered, we show that (1) clock skew increases from about 15% to 30% of the clock cycle, and (2) modeling systematic variation sources enables tighter tolerance design that can substantially reduce this skew as well as reduce wire length limitations.