Different Approaches for Clock Skew Analysis in Present and Future Synchronous IC's

One of the major performance limitations in chip designs is clock skew, the uncertainty in arrival times between a pair of clocks. Clock skew can limit overall circuit performance, or even cause functional errors. The main goal of this paper is to analyse and compare the most popular analytical models for estimating the clock skew for present and future VLSI systems. These models are compared for a generic global clock distribution network (an H-tree) with a JAVA program. Finally based on the presented models, a prevision for the clock skew value in upcoming technology nodes will be given.