Post-CTS delay insertion to fix timing violations

In mainstream ASIC design, industry standard automation tools are used in generating circuit implementations that satisfy the timing and power budgets. A typical timing budget follows the specifications of a clock frequency governed by the longest data path in the circuit. To satisfy this constraint, a zero-skew clock network that minimizes or bounds the clock skew is synthesized. Due to variations, however, zero clock skew cannot always be maintained and timing violations occur. This paper describes a post-clock-tree synthesis (CTS) delay insertion process on the clock tree network in order to fix timing violations that occur after such automated design tools are used. A mathematical formulation is presented which computes the minimum amount of delay to be inserted on each branch of the clock network. Experimental results show that the clock networks of the largest ISCAS’89 circuits can be corrected post-CTS to resolve the timing conflicts in approximately 90% of the circuits with minimal delay insertion (0.159×clock period per clock path on average).