RF Characterization of Square Spiral Inductors on a 0.25 μm Digital CMOS Process

The growth of wireless applications in the low GHz range has been a catalyst in numerous research activities to develop wireless applications in standard digital CMOS processes. The relatively lower costs in developing single chip solutions for wireless applications in CMOS technology is considered its main advantage over other semiconductor processes. Thus, with the integration of RF systems in CMOS, planar inductors will have a dominant role in defining the achievable performance of the system as a whole. The inductors used in this study were used in the input impedance matching for an LNA at 2.4 GHz. Plain square spiral inductors and square spiral inductors with Q enhancement structures are implemented on a 0.25 μm digital CMOS process with inductance values of 1.8 nH and 10 nH. On Wafer RF characterization of the inductors were done using an inductor model proposed by Yue. Results obtained show that parasitic resistance limits the Q of square spiral inductors on a digital CMOS process. Measured results also show how Q enhancement techniques reported in literature affect inductor Q on a digital CMOS process. It is recommended that shunted metals be used in improving inductor Q.