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2002•Unpublished venueRequires access

2 V/100 ns 1 T/1 C nonvolatile ferroelectric memory architecture with bitline-driven read scheme and non-relaxation reference cell

Harutoyo Hirano, Toshiyuki Honda, Norihiko Moriwaki, T. Nakakuma, Akira Inoue, G. Nakane, S. Chaya, Tomonari Sumi

Open publisher page 7 citations

Abstract

Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.

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What this paper is about

Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.

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OpenAlex reports 7 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

Recently, a nonvolatile memory embedded in microcontrollers has been required to have 100 ns access time at 2.0 V for mobile information terminals operating with a re-chargeable battery. To achieve this, this paper proposes new architecture for a ferroelectric nonvolatile memory (FeRAM) comprised of (a) Bitline-Driven Read Scheme and (b) Non-Relaxation Reference Cell for high speed and low voltage operation respectively. Using this architecture, a FeRAM with one transistor and one capacitor per bit (1T/1C) cell can have a performance of 100 ns access time at 2.0 V.

Key concepts: Ferroelectric RAM, Non-volatile memory, Microcontroller, Capacitor, Transistor, Memory cell, Computer science, Ferroelectricity

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