Cost comparison for flip chip, gold wire bond, and copper wire bond packaging
Chet Palesko, E. Jan Vardaman
Abstract
Chet Palesko, E. Jan Vardaman
Abstract
When the cost of gold was $500 per ounce, the lowest cost packaging choice was clear-it was always gold wire bonding. However, with the cost of gold at more than $1,000 per ounce and significant cost decreases in flip chip package fabrication and assembly, the lowest cost packaging choice is no longer obvious. Gold wire bonding is one of the oldest and most mature process, and offers high yields and low processing costs. Copper wire bonding is an alternative to save material cost, but is less mature and requires equipment modifications. Historically, flip chip packages have only been cost effective for area-constrained applications given the additional wafer bumping cost and the high substrate cost. However, wafer bumping costs have decreased significantly in the past few years and low-cost flip chip substrates are now available in the market. This poster presentation will compare the total packaging cost from wafer preparation through final package assembly. The analysis will be done using a comprehensive activity based cost model for each of the three package technologies. All wafer preparation activities (bumping for flip chip, wafer mounting, backgrind, dicing, etc.), substrate fabrication activities (inner layer processing, build-up layer processing, drilling, surface finish, testing, singulation, etc.), and assembly activities (die bonding, wire bonding, underfill, mold compound, lid attach, solder ball attach, etc.) have been modeled and verified using multiple industry sources.
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When the cost of gold was $500 per ounce, the lowest cost packaging choice was clear-it was always gold wire bonding. However, with the cost of gold at more than $1,000 per ounce and significant cost decreases in flip chip package fabrication and assembly, the lowest cost packaging choice is no longer obvious. Gold wire bonding is one of the oldest and most mature process, and offers high yields and low processing costs. Copper wire bonding is an alternative to save material cost, but is less mature and requires equipment modifications. Historically, flip chip packages have only been cost effective for area-constrained applications given the additional wafer bumping cost and the high substrate cost. However, wafer bumping costs have decreased significantly in the past few years and low-cost flip chip substrates are now available in the market. This poster presentation will compare the total packaging cost from wafer preparation through final package assembly. The analysis will be done using a comprehensive activity based cost model for each of the three package technologies. All wafer preparation activities (bumping for flip chip, wafer mounting, backgrind, dicing, etc.), substrate fabrication activities (inner layer processing, build-up layer processing, drilling, surface finish, testing, singulation, etc.), and assembly activities (die bonding, wire bonding, underfill, mold compound, lid attach, solder ball attach, etc.) have been modeled and verified using multiple industry sources.
Key concepts: Bumping, Flip chip, Wire bonding, Wafer dicing, Chip-scale package, Wafer, Integrated circuit packaging, Thermal copper pillar bump