Advances in lithography technologies for wafer-level packaging

With the continuous reduction in IC feature size, the increased demand for higher speed and lower power consumption and with the simultaneous increase of I/O, wafer-level packaging is today an interesting solution for IC and micro electro mechanical systems(MEMS) packaging having as result the cost decrease and increased performance. With wafer-level packaging (WLP) the die and the package are fabricated and tested on the wafer prior to the dicing. Among the advantages of WLP are smaller IC package and a significant of-scale cost reduction due to high throughput of the parallel running packaging and electrical testing steps on wafer size. Thick resist-coating, lithography and wafer-to-wafer alignment for subsequent bonding are key enabling technologies for WLP. The roadmap for transistor scaling predicts further increase of circuit complexity, which comes along with higher pin count densities (pins per unit area) and therefore smaller feature sizes. This fact makes specialized and unique processing equipment development a must. This paper is summarizing the specific process requirements and will review the current technologies supporting WLP.