Technical evaluation of a near chip scale size flip chip/plastic ball grid array package

Technical evaluation and reliability assessment have been performed for a near chip scale size package that utilizes microvias and the Flip Chip-Plastic Ball Grid Array technology. The microvias were photolithographically patterned in a build-up, Surface Laminar Circuit/sup TM/ (SLC) interposer layers. The package accommodated a 12 mm/spl times/14 mm die with 700 controlled collapse chip connections (C4). The carrier dimensions were 21 mm/spl times/21 mm, 1.27 mm pitch with 255 EGA interconnections. The dimensions of the package, for which the target application was microprocessors, conformed to the JEDEC standards. It has been determined that this novel packaging construction is manufacturable and can satisfy the standard reliability requirements.