2003Unpublished venueRequires access

Package characterization and development of a flip chip QFN package: fcMLF

D Mccann, SunHo Ha

Open publisher page 16 citations

Abstract

Describes the performance of a low cost molded package using flip chip interconnections on a copper lead frame substrate. Two flip chip interconnect metallurgies were evaluated: High Pb bumps attached to the lead frame using eutectic Sn37Pb solder paste; Au bumps attached to the leadframe using eutectic Sn3.5Ag solder paste. This package format is identified as the flip chip MicroLeadframe (fcMLF) package family (QFN) in this presentation. Temperature cycle, HAST, storage, and MRT testing were performed. All reliability requirements were achieved. Level 1 260/spl deg/C J-STD-020A moisture classification was achieved. This fcMLF package was also evaluated with and without an exposed thermal pad. Electrical model simulations were completed showing the package was applicable for use up to 40 GHz, depending upon die to package size ratio. Thermal models were completed that demonstrated thermal dissipation of 35/spl deg/C/W theta JA for a 4.00 /spl times/ 4.00 mm body size with an exposed pad.

About this research paper

What this paper is about

Describes the performance of a low cost molded package using flip chip interconnections on a copper lead frame substrate. Two flip chip interconnect metallurgies were evaluated: High Pb bumps attached to the lead frame using eutectic Sn37Pb solder paste; Au bumps attached to the leadframe using eutectic Sn3.5Ag solder paste. This package format is identified as the flip chip MicroLeadframe (fcMLF) package family (QFN) in this presentation. Temperature cycle, HAST, storage, and MRT testing were performed. All reliability requirements were achieved. Level 1 260/spl deg/C J-STD-020A moisture classification was achieved. This fcMLF package was also evaluated with and without an exposed thermal pad. Electrical model simulations were completed showing the package was applicable for use up to 40 GHz, depending upon die to package size ratio. Thermal models were completed that demonstrated thermal dissipation of 35/spl deg/C/W theta JA for a 4.00 /spl times/ 4.00 mm body size with an exposed pad.

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Available abstract

Describes the performance of a low cost molded package using flip chip interconnections on a copper lead frame substrate. Two flip chip interconnect metallurgies were evaluated: High Pb bumps attached to the lead frame using eutectic Sn37Pb solder paste; Au bumps attached to the leadframe using eutectic Sn3.5Ag solder paste. This package format is identified as the flip chip MicroLeadframe (fcMLF) package family (QFN) in this presentation. Temperature cycle, HAST, storage, and MRT testing were performed. All reliability requirements were achieved. Level 1 260/spl deg/C J-STD-020A moisture classification was achieved. This fcMLF package was also evaluated with and without an exposed thermal pad. Electrical model simulations were completed showing the package was applicable for use up to 40 GHz, depending upon die to package size ratio. Thermal models were completed that demonstrated thermal dissipation of 35/spl deg/C/W theta JA for a 4.00 /spl times/ 4.00 mm body size with an exposed pad.

Key concepts: Quad Flat No-leads package, Lead frame, Flip chip, Package on package, Materials science, Chip-scale package, Eutectic system, System in package

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