2014Unpublished venueRequires access

Alternative package-on-package with organic substrate interposer for stacking packaging solution

Steven Lin, Mark Liao, Albert Lan, David Wang

Open publisher page 3 citations

Abstract

Package-on-Package (PoP) is an integrated circuit packaging method to vertically combine discrete logic device and low power mobile memory packages. Two chip scale BGA packages are installed atop each other, i.e. stacked, with a specific interface to route signals between them. This allows higher component density in devices, such as smart phone and tablet hand held products for bottom FCCSP digital Apps Processor, Modem, to stack with top Wire Bond LPPDDR CSP. The bottom FCCSP package form factor and its pin up of top solder balls were limited by LPDDR BGA matrix which had been defined by JEDEC. Due to high bandwidth memory requirement in smart phone, a lot of new PoP package solutions to accommodate more I/Os between top LPDDR memory package and bottom digital application processor package are booming up recently.

About this research paper

What this paper is about

Package-on-Package (PoP) is an integrated circuit packaging method to vertically combine discrete logic device and low power mobile memory packages. Two chip scale BGA packages are installed atop each other, i.e. stacked, with a specific interface to route signals between them. This allows higher component density in devices, such as smart phone and tablet hand held products for bottom FCCSP digital Apps Processor, Modem, to stack with top Wire Bond LPPDDR CSP. The bottom FCCSP package form factor and its pin up of top solder balls were limited by LPDDR BGA matrix which had been defined by JEDEC. Due to high bandwidth memory requirement in smart phone, a lot of new PoP package solutions to accommodate more I/Os between top LPDDR memory package and bottom digital application processor package are booming up recently.

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Available abstract

Package-on-Package (PoP) is an integrated circuit packaging method to vertically combine discrete logic device and low power mobile memory packages. Two chip scale BGA packages are installed atop each other, i.e. stacked, with a specific interface to route signals between them. This allows higher component density in devices, such as smart phone and tablet hand held products for bottom FCCSP digital Apps Processor, Modem, to stack with top Wire Bond LPPDDR CSP. The bottom FCCSP package form factor and its pin up of top solder balls were limited by LPDDR BGA matrix which had been defined by JEDEC. Due to high bandwidth memory requirement in smart phone, a lot of new PoP package solutions to accommodate more I/Os between top LPDDR memory package and bottom digital application processor package are booming up recently.

Key concepts: Package on package, Quad Flat No-leads package, Ball grid array, Chip-scale package, Interposer, System in package, Integrated circuit packaging, Computer science

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