Solder bumping via paste reflow for area array packages

With the electronic industry advancing rapidly toward smaller, lighter, faster, and cheaper products, area array packages including BGAs, CSPs, and flip chips quickly becomes the focus of IC packaging technology, mainly due to the robustness in handling and considerable reduction in size. The solder paste printing and reflow process is a well established robust and cheap process. Obviously, the throughput and the cost of solder bumping could be at least order of magnitude more favorable if a conventional surface mount solder paste printing and reflow process can be employed. Works in this paste bumping process has been rare, and the focus has been on wafer bumping only. In this study, the cost of the paste bumping process is compared with other processes. In addition, solder bumping for BGA, CSP, and wafer via a solder paste print/reflow process with high quality and high yield is demonstrated, and the requirements on solder paste materials and printing parameters are discussed.