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2006•Unpublished venueRequires access

Ultra Thin Hermetic Wafer level, Chip Scale Package

Lior Shiv, M. Heschel, H. Korth, S. Weichel, R. Hauffe, A. Kilian, B. Semak, M. Houlberg, P.N. Egginton, A. Hase, J.F. Kuhmann

Open publisher page 8 citations

Abstract

This paper presents a novel technology for hermetic wafer-level chip size packaging (WLCSP). The ultra thin surface mountable (SMT) package has a small footprint and addresses MEMS and IC applications in the emerging market for handheld devices. Our approach combines through-wafer interconnects (mu-vias), wafer-to-wafer bonding, subsequent thinning and solder bumping to obtain a small form factor package. The latter adds as little as 100 mum to the final device, resulting in a total thickness of 0.5mm or less. The short interconnects enable true chip-size packages as small as 700times700 mum for direct surface mount attach. In the paper we present the packaging concept, detailed description of the process and characterization of the electrical properties and sealing

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What this paper is about

This paper presents a novel technology for hermetic wafer-level chip size packaging (WLCSP). The ultra thin surface mountable (SMT) package has a small footprint and addresses MEMS and IC applications in the emerging market for handheld devices. Our approach combines through-wafer interconnects (mu-vias), wafer-to-wafer bonding, subsequent thinning and solder bumping to obtain a small form factor package. The latter adds as little as 100 mum to the final device, resulting in a total thickness of 0.5mm or less. The short interconnects enable true chip-size packages as small as 700times700 mum for direct surface mount attach. In the paper we present the packaging concept, detailed description of the process and characterization of the electrical properties and sealing

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Available abstract

This paper presents a novel technology for hermetic wafer-level chip size packaging (WLCSP). The ultra thin surface mountable (SMT) package has a small footprint and addresses MEMS and IC applications in the emerging market for handheld devices. Our approach combines through-wafer interconnects (mu-vias), wafer-to-wafer bonding, subsequent thinning and solder bumping to obtain a small form factor package. The latter adds as little as 100 mum to the final device, resulting in a total thickness of 0.5mm or less. The short interconnects enable true chip-size packages as small as 700times700 mum for direct surface mount attach. In the paper we present the packaging concept, detailed description of the process and characterization of the electrical properties and sealing

Key concepts: Bumping, Chip-scale package, Wafer, Wafer-level packaging, Surface-mount technology, Materials science, Chip, Wafer-scale integration

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