Scalability potential in ELTRAN/sup (R)/ SOI-epi wafer

For coming device applications, advanced requirements for silicon-on-insulator (SOI) wafers are increasing. One of the most important items is scalability that includes scaling up of the wafer diameter and scaling down of the SOI layer thickness (t/sub SOI/). 300 mm wafers and ultra thin SOI with t/sub SOI/ less than 100 nm will be required according to the ITRS (SIA, 1999). 300 mm SOI wafers are essential for process cost reduction of the most advanced device applications with shrunken design rules. On the other hand, ultra thin SOI layers are important especially for fully depleted SOI-MOSFETs. In this paper, we applied ELTRAN/sup (R)/ technology (Yonehara et al., 1994) to 300 mm SOI and ultra thin SOI in order to demonstrate the scalability.