Snapback Breakdown Dynamics and ESD Susceptibility of LDMOS

LDMOS transistors are widely used as output drivers in multiple applications in smart power IC designs. Relative to their sizes, LDMOS transistors are inherently weak with respect to ESD reliability and enhancing their ESD robustness has been an on-going challenge for many years. Snapback breakdown in MOSFET devices has been widely employed to explain the device failures due to ESD. A figure depicts a typical I-V characteristic and the testing device leakage evolution for a MOSFET device subject to transmission-line-pulse (TLP) ESD stress. For most conventional MOSFET devices, the first snapback breakdown, defined It1and Vt1, is not a threat to the device until it reaches its thermal limit, It2. For most LDMOS cases, however, the first snapback breakdown can lead to the device damage. It has been broadly accepted that non-uniform snapback breakdown leads to current filamentation/crowding, which leads to excessive heating and failure. For a given type of LDMOS, two different failure modes are observed, which is dependent upon the effective gate width. A description and explanation of the different failure mechanisms due to these effects on the devices with different geometry is provided