ESD Scalability of LDMOS Devices for Self-Protected Output Drivers

Lateral DMOS (LDMOS) power transistors of SMART technologies are widely used as output drivers in multiple applications. However, LDMOS devices are generally not robust under ESD due to deep snapback causing localized current crowding and leading to inhomogeneous triggering of the parasitic bipolar, ESD ruggedness of LDMOS power devices has been a significant subject in smart power IC technology. Lack of understanding in geometry scalability of the LDMOS devices often thwarts a proper implementation of self-protected structures. Therefore, it is necessary to understand the ESD scalability and failure mechanism of the power output devices to meet various levels of design requirement and optimize ESD protection solution. LDMOS devices ESD capability has been understood from snapback breakdown of the parasitic bipolar components. They usually show different behavior under ESD stress conditions, compared to the normal MOS transistors. The triggering mechanism of the snapback breakdown has been major subjects in terms of device structures and designs. In this paper, we report an ESD capability and scalability of the LDMOS devices from the geometry and operational aspects, employing both experimental and simulation data. Difference of transient electrical behaviors and failure mechanisms of DMOS with different geometries under ESD stress conditions is also addressed