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1972•IEEE Journal of Solid-State CircuitsRequires access

Shunt-feedback Schottky clamped logic gates

David Kan

Open publisher page 1 citations

Abstract

A new approach to digital circuit design is used to develop a new family of TTL-compatible shunt-feedback Schottky clamped logic gates. The virtual ground like input of the shunt-feedback amplifier and the low-impedance input of the familiar diode-biased current source are utilized to perform certain logic and fan-out operations without requiring full logic swings. Voting logic operations as well as conventional Boolean logic operations, such as AND, NAND, OR, NOR, AND-OR, AOI, etc., can all be performed with approximately the same one-gate delay of 2.5 ns. Average dissipation of the NAND gate is 17 mW. The series-terminated transmission-line connection without requiring full logic swing is described.

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What this paper is about

A new approach to digital circuit design is used to develop a new family of TTL-compatible shunt-feedback Schottky clamped logic gates. The virtual ground like input of the shunt-feedback amplifier and the low-impedance input of the familiar diode-biased current source are utilized to perform certain logic and fan-out operations without requiring full logic swings. Voting logic operations as well as conventional Boolean logic operations, such as AND, NAND, OR, NOR, AND-OR, AOI, etc., can all be performed with approximately the same one-gate delay of 2.5 ns. Average dissipation of the NAND gate is 17 mW. The series-terminated transmission-line connection without requiring full logic swing is described.

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Available abstract

A new approach to digital circuit design is used to develop a new family of TTL-compatible shunt-feedback Schottky clamped logic gates. The virtual ground like input of the shunt-feedback amplifier and the low-impedance input of the familiar diode-biased current source are utilized to perform certain logic and fan-out operations without requiring full logic swings. Voting logic operations as well as conventional Boolean logic operations, such as AND, NAND, OR, NOR, AND-OR, AOI, etc., can all be performed with approximately the same one-gate delay of 2.5 ns. Average dissipation of the NAND gate is 17 mW. The series-terminated transmission-line connection without requiring full logic swing is described.

Key concepts: Pass transistor logic, NAND gate, Logic family, Logic gate, Emitter-coupled logic, Resistor–transistor logic, Logic level, AND-OR-Invert

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