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SPL (super push-pull logic) a bipolar novel low-power high-speed logic circuit

Usami, Shiozawa

Abstract

In this contribution we would like to present a new bipolar low -power high -speed logic circuit named SPL (Super Push-pull Logic). At a low POY~~ per gate range of lmw/gate, the calculated path propagation delay time of SPL gates loading wire capacitances of 0.57pF/gate is 2.75 times faster than the one of conventional ECL(Emitter Coupled Logic) gates.

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Available abstract

Key concepts: Emitter-coupled logic, Pass transistor logic, Logic gate, Resistor–transistor logic, Logic family, AND-OR-Invert, Diode–transistor logic, Electrical engineering