1989IEEE Transactions on Electron DevicesRequires access

Application of AlGaAs/GaAs HBTs to high-speed CML logic family fabrication

Mohammad Madihian, Shōji Tanaka, N. Hayama, A. Okamoto, K. Honjo

Open publisher page 5 citations

Abstract

Discusses the design, fabrication, and performance of the first small-scale integrated logic family, including a current-mode-logic (CML)N inverter, OR/NOR, NAND/OR. exclusive OR/NOR gates, and master-slave flip-flops, implemented using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs). The HBTs incorporated in the ICs (integrated circuits) are based on a 2.5- mu m emitter design rule and exhibit a current gain of 40, a cutoff frequency of 50 GHz, an estimated CML gate-propagation delay time of 24.7 ps, and a non-threshold-logic gate-propagation delay time of 12.3 ps. Successful operation of the logic circuits has been predicted using a SPICE-F simulator and verified experimentally.>

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What this paper is about

Discusses the design, fabrication, and performance of the first small-scale integrated logic family, including a current-mode-logic (CML)N inverter, OR/NOR, NAND/OR. exclusive OR/NOR gates, and master-slave flip-flops, implemented using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs). The HBTs incorporated in the ICs (integrated circuits) are based on a 2.5- mu m emitter design rule and exhibit a current gain of 40, a cutoff frequency of 50 GHz, an estimated CML gate-propagation delay time of 24.7 ps, and a non-threshold-logic gate-propagation delay time of 12.3 ps. Successful operation of the logic circuits has been predicted using a SPICE-F simulator and verified experimentally.>

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Available abstract

Discusses the design, fabrication, and performance of the first small-scale integrated logic family, including a current-mode-logic (CML)N inverter, OR/NOR, NAND/OR. exclusive OR/NOR gates, and master-slave flip-flops, implemented using self-aligned AlGaAs/GaAs heterojunction bipolar transistors (HBTs). The HBTs incorporated in the ICs (integrated circuits) are based on a 2.5- mu m emitter design rule and exhibit a current gain of 40, a cutoff frequency of 50 GHz, an estimated CML gate-propagation delay time of 24.7 ps, and a non-threshold-logic gate-propagation delay time of 12.3 ps. Successful operation of the logic circuits has been predicted using a SPICE-F simulator and verified experimentally.>

Key concepts: Emitter-coupled logic, Inverter, NAND gate, NOR gate, Heterojunction bipolar transistor, Logic gate, Resistor–transistor logic, Current-mode logic

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