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1999•IEEE Transactions on Circuits and Systems II Analog and Digital Signal ProcessingRequires access

Sigma-delta ADC with reduced sample rate multibit quantizer

Wei Qin, Bo Hu, Xieting Ling

Open publisher page 15 citations

Abstract

Based on the well-known Leslie-Singh architecture, a new cascaded sigma-delta analog-to-digital conversion (ADC) architecture is proposed. It incorporates a multibit quantizer whose sample rate can be significantly lower than the full oversampling speed of the sigma-delta modulator. Simulation results and comparison with other architectures are given. The architecture can be a good choice to extend the use of sigma-delta ADC to high bandwidth applications.

About this research paper

What this paper is about

Based on the well-known Leslie-Singh architecture, a new cascaded sigma-delta analog-to-digital conversion (ADC) architecture is proposed. It incorporates a multibit quantizer whose sample rate can be significantly lower than the full oversampling speed of the sigma-delta modulator. Simulation results and comparison with other architectures are given. The architecture can be a good choice to extend the use of sigma-delta ADC to high bandwidth applications.

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OpenAlex reports 15 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

Based on the well-known Leslie-Singh architecture, a new cascaded sigma-delta analog-to-digital conversion (ADC) architecture is proposed. It incorporates a multibit quantizer whose sample rate can be significantly lower than the full oversampling speed of the sigma-delta modulator. Simulation results and comparison with other architectures are given. The architecture can be a good choice to extend the use of sigma-delta ADC to high bandwidth applications.

Key concepts: Oversampling, Delta-sigma modulation, Sigma, Bandwidth (computing), Architecture, Electronic engineering, Computer science, Mathematics

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