High-performance instruction-set simulator for TMS320C62x DSP

The instruction-set simulator (ISS) for DSP is essential to the exploration of DSP micro-architecture and DSP-centric system, just as that for the general-purpose processor. As the mainstream DSPs have developed instruction-level parallelism via very-long instruction word (VLIW), greater challenges are facing design of such simulators than that for superscalar ones. The ISSs not only define the behavior but also have to depict the timing of each instruction exactly at level of pipeline-cycle, which leads to performance penalty consequentially. A high-performance ISS has been proposed for TMS320C62x DSP, a VLIW-based DSP from TI. The proposed one has employed a unified and parameterized scheme to define all kinds of timing information, including timing of instruction-issue, delay-slot, etc. As compared to the conventional pipeline-based simulator, the proposed one was shown to achieve higher performance by more than 40%.