AN EVALUATION OF A CONFIGURABLE VLIW MICROARCHITECTURE FOR EMBEDDED DSP APPLICATIONS

The last decade has witnessed a significant increase in processor offerings geared towards embedded DSP applications. Such processors are commonly VLIW architectures with special ISA and/or microarchitecture features for speeding up signal processing functions and customization options to improve cost/performance. The Jazz Programmable System Architecture from Improv Systems is one such processor offering. Jazz employs a VLIW architecture which is well-suited to the characteristics of embedded DSP applications such as voice over packet, media processing, and home connectivity. The microarchitecture incorporates overlaid datapaths, distributed register file and memory systems, code compression, and parallel computation and memory access. Jazz permits design-time configuration in an attempt to bridge the gap between the flexibility of a programmable processor and the cost-benefit of full customization. In this paper, we explore the cost/performance tradeoffs of the Jazz microarchitecture on various embedded multimedia applications using a detailed cycle-level simulator as well as area and power models. Through a comparison of the performance, power, and area of different hardware configurations running these applications, we demonstrate how the configurability of the architecture affords a cost-performance benefit over a fixed microarchitecture. Key features of the microarchitecture are quantitatively evaluated in terms of their influence on performance. The relationship between compiler optimizations and processor performance is also explored.