Steve P. Landry
Abstract
Logic cell arrays allow ASIC designers to create new logic elements and to devise symbols for them that simplify logic schematics.
OpenAlex reports 3 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
Logic cell arrays allow ASIC designers to create new logic elements and to devise symbols for them that simplify logic schematics.
Key concepts: Computer science, Logic family, Logic synthesis, Logic optimization, Logic gate, Resistor–transistor logic, Register-transfer level, Application-specific integrated circuit