Logic Synthesis of Sequential Logic Circuits for Adiabatic Quantum-Flux-Parametron Logic

The adiabatic quantum-flux-parametron (AQFP) superconductor logic family has the potential to be the electronics groundwork for energy-efficient large-scale computing. To this end, we have been developing an AQFP top-down design flow, and our design efficiency has improved recently for combinational logic circuits. As a next step, we establish a methodology to synthesize sequential logic circuits which we previously did not consider. In this paper, we describe our sequential logic circuit model and how it can be used to map the sequential elements of an RTL (register transfer level) behavioral design. Next we discuss the structure of sequential circuits in more detail using a benchmark of N-bit counters. Lastly, we show some preliminary results of a synthesized 16 bit MIPS microprocessor. During this study, we also developed an architectural retiming methodology to reduce the number of synchronization buffers needed for microprocessor pipeline stage balancing.