Design of Frequency Synthesizer Based on DDS + PLL Technology
Qing Wu, Shen Kai
Abstract
Qing Wu, Shen Kai
Abstract
This paper presents a design plan for the frequency synthesizer base on DDS and PLL of the digital receiver, the main hardware selection is shown. Finally through the system test, the results show that the frequency accuracy of the frequency synthesizer reaches 3.72×10-8, the resolution is 1Hz, the phase noise is 103dBc/Hz@1 kHz the clutter rejection is 67dB and the frequency conversion time reaches 9.6ms. This frequency synthesizer can produce low phase noise, high resolution and high stability of the broadband signal. It has excellent technical performance, has been widely used in engineering.
OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.
A contribution statement is not available in the OpenAlex record.
Method details are not available in the OpenAlex metadata.
Findings are not separately available in the OpenAlex metadata.
Limitations are not available in the OpenAlex metadata.
Application details are not available in the OpenAlex metadata.
This paper presents a design plan for the frequency synthesizer base on DDS and PLL of the digital receiver, the main hardware selection is shown. Finally through the system test, the results show that the frequency accuracy of the frequency synthesizer reaches 3.72×10-8, the resolution is 1Hz, the phase noise is 103dBc/Hz@1 kHz the clutter rejection is 67dB and the frequency conversion time reaches 9.6ms. This frequency synthesizer can produce low phase noise, high resolution and high stability of the broadband signal. It has excellent technical performance, has been widely used in engineering.
Key concepts: Frequency synthesizer, Direct digital synthesizer, Phase-locked loop, Phase noise, PLL multibit, Electronic engineering, Broadband, Computer science