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2006•Unpublished venueRequires access

Design and Analysis of the S-band PLL Frequency Synthesizer with Low Phase Noise

Haihong Ma, Xiao Tang, Fei Xiao, Chizhou Tan

Open publisher page 6 citations

Abstract

Controlled by a single chip, the S-band PLL frequency synthesizer at 2.82GHz with low phase noise is designed. Based on the study of PLL, the requirements for the phase noise of the crystal reference oscillator are theoretically estimated. And an effective method to completely eliminate the spurs caused by the single chip is presented. The phase noise of 2.82GHz PLL frequency synthesizer at 10 kHz offset is -94.3dBc/Hz, the reference spurs is better than -90dBc and the output power is over 18dBm.

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What this paper is about

Controlled by a single chip, the S-band PLL frequency synthesizer at 2.82GHz with low phase noise is designed. Based on the study of PLL, the requirements for the phase noise of the crystal reference oscillator are theoretically estimated. And an effective method to completely eliminate the spurs caused by the single chip is presented. The phase noise of 2.82GHz PLL frequency synthesizer at 10 kHz offset is -94.3dBc/Hz, the reference spurs is better than -90dBc and the output power is over 18dBm.

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Available abstract

Controlled by a single chip, the S-band PLL frequency synthesizer at 2.82GHz with low phase noise is designed. Based on the study of PLL, the requirements for the phase noise of the crystal reference oscillator are theoretically estimated. And an effective method to completely eliminate the spurs caused by the single chip is presented. The phase noise of 2.82GHz PLL frequency synthesizer at 10 kHz offset is -94.3dBc/Hz, the reference spurs is better than -90dBc and the output power is over 18dBm.

Key concepts: Phase-locked loop, Phase noise, PLL multibit, Frequency synthesizer, Offset (computer science), Electronic engineering, Direct digital synthesizer, Phase frequency detector

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