Design of C Band PLL Frequency Synthesizer
Zhou Yi-guo
Abstract
Zhou Yi-guo
Abstract
C band frequency synthesizer is presented.The design is based on digital phase locked loop(PLL)technology.The output of the frequency synthesizer is 6.4 GHz,with the power 10 dBm,and phase noise better than-74.1 dBc/Hz@1 kHz.The frequency synthesizer can be used widely in the communication and test systems.
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C band frequency synthesizer is presented.The design is based on digital phase locked loop(PLL)technology.The output of the frequency synthesizer is 6.4 GHz,with the power 10 dBm,and phase noise better than-74.1 dBc/Hz@1 kHz.The frequency synthesizer can be used widely in the communication and test systems.
Key concepts: Phase-locked loop, Frequency synthesizer, dBc, Direct digital synthesizer, PLL multibit, Phase noise, Electronic engineering, Frequency multiplier