ScholarLens Back to search
2013•Unpublished venueRequires access

ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process

Chang-Tzu Wang, Yi‐Chun Chen, Tien-Hao Tang, Kuan-Cheng Su

Open publisher page 1 citations

Abstract

An N-channel electrostatic discharge (ESD) protection device with DNW sinker has been designed without latch-up risk for 5-V operating condition. With the DNW sinker, the NMOS snapback behavior can be restrained and the holding voltage can be increased. The proposed ESD protection device can sustain 3.6kV human-body-model (HBM) and 325V machine model (MM) ESD tests. With holding voltage of 6.4V, the latch-up test shows the immunity from 7.5V voltage test and 200-mA current test.

About this research paper

What this paper is about

An N-channel electrostatic discharge (ESD) protection device with DNW sinker has been designed without latch-up risk for 5-V operating condition. With the DNW sinker, the NMOS snapback behavior can be restrained and the holding voltage can be increased. The proposed ESD protection device can sustain 3.6kV human-body-model (HBM) and 325V machine model (MM) ESD tests. With holding voltage of 6.4V, the latch-up test shows the immunity from 7.5V voltage test and 200-mA current test.

Why it matters

OpenAlex reports 1 citations for this work. Citation counts describe recorded attention and do not establish research quality.

Key contribution

A contribution statement is not available in the OpenAlex record.

Method / approach

Method details are not available in the OpenAlex metadata.

Main findings

Findings are not separately available in the OpenAlex metadata.

Limitations

Limitations are not available in the OpenAlex metadata.

Applications

Application details are not available in the OpenAlex metadata.

Available abstract

An N-channel electrostatic discharge (ESD) protection device with DNW sinker has been designed without latch-up risk for 5-V operating condition. With the DNW sinker, the NMOS snapback behavior can be restrained and the holding voltage can be increased. The proposed ESD protection device can sustain 3.6kV human-body-model (HBM) and 325V machine model (MM) ESD tests. With holding voltage of 6.4V, the latch-up test shows the immunity from 7.5V voltage test and 200-mA current test.

Key concepts: Snapback, Electrostatic discharge, NMOS logic, Voltage, CMOS, Electrical engineering, Human-body model, Engineering

Related papers

Related paper 1Related paper 2Related paper 3
Back to paper searchBrowse research topicsOriginal source
ESD protection design with adjustable snapback behavior for 5-V application in 100nm CMOS process — Research Paper | ScholarLens