Integrate custom layout with ASIC back-end design flow for high performance datapath design

A method to integrate custom layout with ASIC back-end flow for high performance datapath design is introduced in this paper. It combines custom physical design techniques with conventional standard-cell based timing-driven back-end design flow. The results of two subchip design cases using this method for datapath circuits and implemented based on Fujitsu 90 nm process are presented, achieving advantages such as high area utilization, good speed, and low power consumption while ensuring timing continuous convergence.