2008•Microelectronics JournalRequires access

Application of a combined methodology for extraction of the electrical model of a lead frame chip-scale package

Eoin Mc Gibney, John Barrett

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Key concepts: Parasitic extraction, Lead frame, Quad Flat No-leads package, Chip-scale package, Electronic engineering, Chip, Interconnection, Signal integrity

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Application of a combined methodology for extraction of the electrical model of a lead frame chip-scale package — Research Paper | ScholarLens