2002Unpublished venueRequires access

S-pad implementation; total plastic package crack solution for non-moisture sensitive package

Noritsugu Umehara, S. Inomata, Yuji Umeda, M. Naeshiru, Kan Sakamoto

Open publisher page 7 citations

Abstract

This paper investigates capability of following technologies; mold compound, die attach adhesive, textured die pad, and buffer coat, in resolving or improving the package crack performance of plastic package during reflow soldering process. We have finally succeeded in resolving this problem by making a die pad smaller than chip size and analyzed the stress, thermal and electrical characterization by using the simulation to determine suitable scoop size and lead frame line-up. The chip size limitation was confirmed by actual experiments for a chip size, a package size and a package thickness.

About this research paper

What this paper is about

This paper investigates capability of following technologies; mold compound, die attach adhesive, textured die pad, and buffer coat, in resolving or improving the package crack performance of plastic package during reflow soldering process. We have finally succeeded in resolving this problem by making a die pad smaller than chip size and analyzed the stress, thermal and electrical characterization by using the simulation to determine suitable scoop size and lead frame line-up. The chip size limitation was confirmed by actual experiments for a chip size, a package size and a package thickness.

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OpenAlex reports 7 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper investigates capability of following technologies; mold compound, die attach adhesive, textured die pad, and buffer coat, in resolving or improving the package crack performance of plastic package during reflow soldering process. We have finally succeeded in resolving this problem by making a die pad smaller than chip size and analyzed the stress, thermal and electrical characterization by using the simulation to determine suitable scoop size and lead frame line-up. The chip size limitation was confirmed by actual experiments for a chip size, a package size and a package thickness.

Key concepts: Lead frame, Quad Flat No-leads package, Chip-scale package, Die (integrated circuit), Package on package, Materials science, Soldering, Integrated circuit packaging

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