Copper pillar bumped sapphire flip chip on lead-frame package development
Zhiyuan Yang John
Abstract
Zhiyuan Yang John
Abstract
In the development of copper pillar bumped sapphire flip chip on lead-frame package (FCOLF), the die was found very vulnerable in assembly process. In the package reliability test the bump connection opened on the die side where the failure was initiated with cracks on die re-passivation layer. In order to find the root cause, comprehensive investigations have been carried out on wafer bumping quality check, bump and package structure finite element analysis as well as assembly process test etc. The results of the analysis & experiment as well as the process solution for volume production are presented in this paper.
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In the development of copper pillar bumped sapphire flip chip on lead-frame package (FCOLF), the die was found very vulnerable in assembly process. In the package reliability test the bump connection opened on the die side where the failure was initiated with cracks on die re-passivation layer. In order to find the root cause, comprehensive investigations have been carried out on wafer bumping quality check, bump and package structure finite element analysis as well as assembly process test etc. The results of the analysis & experiment as well as the process solution for volume production are presented in this paper.
Key concepts: Bumping, Lead frame, Flip chip, Thermal copper pillar bump, Chip-scale package, Die (integrated circuit), Quad Flat No-leads package, Wafer testing