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2012•2012 4th Electronic System-Integration Technology ConferenceRequires access

3D SiP module using TSV and novel low-volume solder-on-pad(SoP) process

Hyun‐Cheol Bae, Ho-Eun Bae, Su-Jeong Jeon, Kwang-Hoon Jung, Yong‐Sung Eom, Kwang‐Seong Choi

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Abstract

In this paper, a three-dimensional system in packaging (3D SiP) module in which a bottom interposer and a top interposer are interconnected vertically with the low-volume solder-on-pad (SoP) and through-silicon vias (TSVs) has been presented. A novel solder bumping material has been developed for the low-volume SoP and the thickness of SoP was measured about 10 μm. The low-volume SoP was evaluated by the cross-sectional photographs and the measurement of dc resistance using daisy-chain patterns. 3D SiP module composed of a GPU and two SRAM on the interposers were fabricated with this bumping material, a fluxless underfill and the vertical interconnection processes.

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What this paper is about

In this paper, a three-dimensional system in packaging (3D SiP) module in which a bottom interposer and a top interposer are interconnected vertically with the low-volume solder-on-pad (SoP) and through-silicon vias (TSVs) has been presented. A novel solder bumping material has been developed for the low-volume SoP and the thickness of SoP was measured about 10 μm. The low-volume SoP was evaluated by the cross-sectional photographs and the measurement of dc resistance using daisy-chain patterns. 3D SiP module composed of a GPU and two SRAM on the interposers were fabricated with this bumping material, a fluxless underfill and the vertical interconnection processes.

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Available abstract

In this paper, a three-dimensional system in packaging (3D SiP) module in which a bottom interposer and a top interposer are interconnected vertically with the low-volume solder-on-pad (SoP) and through-silicon vias (TSVs) has been presented. A novel solder bumping material has been developed for the low-volume SoP and the thickness of SoP was measured about 10 μm. The low-volume SoP was evaluated by the cross-sectional photographs and the measurement of dc resistance using daisy-chain patterns. 3D SiP module composed of a GPU and two SRAM on the interposers were fabricated with this bumping material, a fluxless underfill and the vertical interconnection processes.

Key concepts: Bumping, Interposer, System in package, Interconnection, Soldering, Materials science, Ball grid array, Package on package

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3D SiP module using TSV and novel low-volume solder-on-pad(SoP) process — Research Paper | ScholarLens