2013•Unpublished venueRequires access
Intrinsic dielectric stack reliability of a high performance bulk planar 20nm replacement gate high-k metal gate technology and comparison to 28nm gate first high-k metal gate process
William E. McMahon, C. Tian, Suresh Uppal, H. Kothari, Minjung Jin, G. LaRosa, T. Nigam, A. Kerber, B.P. Linder, E. Cartier, W. Lai, Y. Liu, Rahul Ramachandran, U. Kwon, B. Parameshwaran, Siddarth Krishnan, Vijay Narayanan
Open publisher page 13 citations
Abstract
We compare the intrinsic reliability of the dielectric stack of a high performance bulk planar 20nm replacement gate technology to the reliability of high performance bulk planar 28 nm gate first high-k metal gate (HKMG) technology, developed within the IBM Alliance. Comparable N/PFET TDDB and comparable/improved NFET PBTI are shown to be achievable for similar Tinv. The choice to not include channel silicon germanium as a PFET performance element in the 20nm technology impact NBTI, driving a potential tradeoff between NBTI and PBTI. The complexity of integrating such performance elements while accounting for reliability/performance tradeoffs demands their selection during technology definition with due consideration to realistic product usage conditions.