2008Unpublished venueRequires access

SPICE modelling of the superjunction IGBT

Marina Antoniou, Florin Udrea, F. Bauer

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Abstract

This paper presents a SPICE model of the Superjunction Insulated Gate Bipolar Transistor (SJIGBT). SPICE simulation results are in good agreement with the DESSIS simulation results under DC conditions. This model consists of an intrinsic MOSFET and a parallel combination of a wide and a narrow base pnp BJTs. A parasitic JFET is also included to account for the restricted current flow between two adjacent p-wells. In addition the JFET component also models the additional depletion region caused by the transverse junction at the upper side of the n-drift region where the current is mainly transported via majority carriers.

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What this paper is about

This paper presents a SPICE model of the Superjunction Insulated Gate Bipolar Transistor (SJIGBT). SPICE simulation results are in good agreement with the DESSIS simulation results under DC conditions. This model consists of an intrinsic MOSFET and a parallel combination of a wide and a narrow base pnp BJTs. A parasitic JFET is also included to account for the restricted current flow between two adjacent p-wells. In addition the JFET component also models the additional depletion region caused by the transverse junction at the upper side of the n-drift region where the current is mainly transported via majority carriers.

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Available abstract

This paper presents a SPICE model of the Superjunction Insulated Gate Bipolar Transistor (SJIGBT). SPICE simulation results are in good agreement with the DESSIS simulation results under DC conditions. This model consists of an intrinsic MOSFET and a parallel combination of a wide and a narrow base pnp BJTs. A parasitic JFET is also included to account for the restricted current flow between two adjacent p-wells. In addition the JFET component also models the additional depletion region caused by the transverse junction at the upper side of the n-drift region where the current is mainly transported via majority carriers.

Key concepts: JFET, Spice, Insulated-gate bipolar transistor, MOSFET, Bipolar junction transistor, Electrical engineering, Transistor, Electronic engineering

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