Stability analysis of 6T SRAM cell for nano scale FD-SOI technology

SRAM area is about to exceed 90% of overall chip area to satisfy the increased chip functionality demand. Smaller transistor dimensions increases chip density. At these nano technology nodes variation in Process, voltage, and Temperature (PVT) affects the stability of SRAM cell. This paper investigates six transistors (6T) SRAM stability in hold/standby, read, and write mode design consider SOI MOSFET at 32nm technological node. This paper firstly reviews different techniques to find Static Noise Margin (SNM), read margin, and write margin has been discussed. The effect of PVT parameters and word line voltage on SRAM stability is analyzed in standby and read mode. Scaling VDD from 0.5V to 0.9V, the read stability increase 60% and standby stability increase 129%. When the cell ratio changes from 1 to 3 the stability of SRAM during read mode gets doubled. This paper also investigate the DRV during standby and read mode which is the minimum voltage required to hold or read data, any voltage below DRV can flip the state of SRAM. The DRV 6T SOI SRAM in Standby mode is 0.07V and that in read mode is 0.08V.