SRAM design in fully-depleted SOI technology

Continued increase in variability is a challenge for SRAM scaling into sub-22 nm nodes, and presents an opportunity for the introduction of alternate technologies. In this work, the performance and threshold-voltage variability of vertical SOI finFETs are compared against those of planar fully depleted (FD) SOI MOSFETs with thin buried oxide, and are presented as an alternative to planar bulk CMOS. Analytical modeling derived from 3D device simulations is used to estimate six-transistor SRAM cell performance and yield metrics.