An implementation of ultra-low-stand by power SRAMs using 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT

In 65-nm Silicon-on-Thin-Box (SOTB) technology [1, 2], we demonstrate fully functional embedded single-port (SP) SRAM and dual-port (DP) SRAM for Smart IoT applications [3, 4]. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit ultra-low standby power for SP SRAM is observed, which is reduced to 1/1000 compared to the normal standby mode. The measured read access time of SP SRAM with forward BB is less than 2.0 ns at 1.0 V overdrive and 25°C, which is over 2.5∗ faster than that of normal mode at 0.75 V with zero-BB, achieving over 380 MHz operation. Besides, we propose the localized adoptive wordline width control in SP SRAM, reducing up to 20% active read power. Read/write disturbance issues in DP SRAM are also evaluated by test chips, confirmed there are no issues.