Low power dual edge triggered flip-flop

A new technique for pulse generation circuit of dual edge triggered flip flop for low power is presented in this paper which enables the flip flop to be operated at 1.2 V. By incorporating a new fast latch and employing conditional pre-charging, dual edge triggered flip flop is capable of achieving low power consumption that has smaller delay. According to simulation on Spectre simulator, it has been observed that total power consumption of proposed flip flop at 0.67 switching activity is 30.16% and 27.36% less than that of previous arts DSPFF and SCDFF respectively. Clock-gated sense-amplifier is incorporated to reduce power consumption at low switching activity. Proposed flip-flop is capable to reduce Clock to output delay up to 44% of that of DSPFF.