Ultra low voltage CMOS

Power dissipation is one of the major design concerns for nano-scale CMOS systems. In this talk I will first present ultra low voltage design challenges for both logic and memory considering different levels of design abstraction — device, circuit, and architecture. In the second part of the talk, I will present ultra-dynamic voltage scaling to have the maximum dynamic range of Vdd. Such adaptive supply scaling can provide the required performance at minimum power dissipation under varied load condition.