A Novel Adiabatic Technique for Energy Efficient Logic Circuits Design

As we are moving ahead in technology, the sizes of various gadgets and devices is reducing which means we need to size down the CMOS logic cells. Adiabatic logic circuits are one of the most efficient technologies that are being used today to minimise power consumption. Different adiabatic logic families such as ECRL, 2N-2N2P and PFAL are investigated in this paper. All simulations have been carried out with W/L ratio of all the circuits kept same for fair comparison of results. HSPICE has been used at 65nm technology with supply voltage of 1V at 100MHz frequency, finally plotting of average power dissipation characteristics have been done with the help of a graph and different logic families' comparisons have been done.