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2015•Unpublished venueRequires access

Overview of methods to increase linearity of high-performance ADC

Hua Fan, Kehong Liu, Airong Liu, Lishan Lv, Zhiliang Qiao, Qiang Li

Open publisher page 2 citations

Abstract

This paper makes a review of main methods to improve the linearity of ADCs. Methods are collected in view of mainstream techniques. A model of redundant noise-shaping Pipelined Flash-SAR ADC is proposed, which is the combination of Flash, Pipeline, SAR and ΣΔ ADC, the effectiveness of the model is demonstrated by simulation. Also, application of dynamic element matching (DEM) linearization techniques to the ΣΔ ADC is verified in a third-order four-bit continuous-time ΣΔ modulator with a standard deviation of 1%. Finally, auxiliary DAC calibration technique to improve the linearity of ADC is verified by a concrete 12-bit SAR ADC chip.

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What this paper is about

This paper makes a review of main methods to improve the linearity of ADCs. Methods are collected in view of mainstream techniques. A model of redundant noise-shaping Pipelined Flash-SAR ADC is proposed, which is the combination of Flash, Pipeline, SAR and ΣΔ ADC, the effectiveness of the model is demonstrated by simulation. Also, application of dynamic element matching (DEM) linearization techniques to the ΣΔ ADC is verified in a third-order four-bit continuous-time ΣΔ modulator with a standard deviation of 1%. Finally, auxiliary DAC calibration technique to improve the linearity of ADC is verified by a concrete 12-bit SAR ADC chip.

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OpenAlex reports 2 citations for this work. Citation counts describe recorded attention and do not establish research quality.

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Available abstract

This paper makes a review of main methods to improve the linearity of ADCs. Methods are collected in view of mainstream techniques. A model of redundant noise-shaping Pipelined Flash-SAR ADC is proposed, which is the combination of Flash, Pipeline, SAR and ΣΔ ADC, the effectiveness of the model is demonstrated by simulation. Also, application of dynamic element matching (DEM) linearization techniques to the ΣΔ ADC is verified in a third-order four-bit continuous-time ΣΔ modulator with a standard deviation of 1%. Finally, auxiliary DAC calibration technique to improve the linearity of ADC is verified by a concrete 12-bit SAR ADC chip.

Key concepts: Linearity, Successive approximation ADC, Computer science, Flash ADC, Spurious-free dynamic range, Linearization, Pipeline (software), Comparator

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