A 4.1-bit, 20 GS/s comparator for high speed flash ADC in 45 nm CMOS technology

A 4. -bit, high speed comparator for high-speed flash analog-to-digital converter and K-band applications that can work at a sampling rate of 0GS/s is presented in this paper. This fully differential comparator consists of three stages using a new structure to improve its performance. The offset voltage of the designed comparator has been reduced by means of an active positive feedback. The CMOS positive feedback and a new structure as output circuit are used to improve sampling rate and performance of comparator. The analyses and simulation results were obtained by using CMOS parameters. The comparator can operate with a V peak to peak input range consuming 0.56 mW. The predicted performance is verified by analyses and simulations using HSPICE tool.